git @ Cat's Eye Technologies ZOWIE / 2e897e3
Refactor to use better names. Chris Pressey 6 months ago
2 changed file(s) with 86 addition(s) and 79 deletion(s). Raw diff Collapse all Expand all
+0
-79
impl/ZOWIE.hs/ZOWIE.hs less more
0 module ZOWIE where
1
2 import qualified Data.Map.Strict as Map
3
4
5 type Addr = Integer
6 type Value = Integer
7 type Memory = Map.Map Addr Value
8
9 readMem mem addr = Map.findWithDefault 0 addr mem
10 writeMem mem addr value = Map.insert addr value mem
11
12 type CPU = Integer
13
14 data State = State {
15 cpu :: CPU,
16 mem :: Memory
17 } deriving (Show, Ord, Eq)
18
19
20 readAddr :: State -> Addr -> IO Value
21 readAddr state@State{ cpu=cpu, mem=mem } addr =
22 case addr of
23 0 -> do -- TtyRegister
24 i <- readLn
25 return i
26 1 -> return 1 -- BeginTransactionRegister
27 2 -> return 2 -- CommitRegister
28 3 -> return 3 -- CommitAndRepeatRegister
29 4 -> return 4 -- AdditionRegister
30 5 -> return 5 -- SubtractionRegister
31 6 -> return 6 -- MultiplicationRegister
32 7 -> return 7 -- NegationRegister
33 x -> return (readMem mem x)
34
35
36 writeAddr :: State -> Addr -> Value -> IO State
37 writeAddr state@State{ cpu=cpu, mem=mem } addr payload =
38 case addr of
39 0 -> do -- TtyRegister
40 print payload
41 return state
42 1 -> do -- BeginTransactionRegister
43 return state{ cpu=(beginTransaction cpu) }
44 2 -> let -- CommitRegister
45 cpu' = if payload > 0 then commit cpu else rollback cpu
46 in
47 return state{ cpu=cpu' }
48 3 -> let -- CommitAndRepeatRegister
49 cpu' = if payload > 0 then commitAndRepeat cpu else commit cpu
50 in
51 return state{ cpu=cpu' }
52 4 -> let -- AdditionRegister
53 mem' = writeMem mem 8 ((readMem mem 8) + payload)
54 in
55 return state{ mem=mem' }
56 5 -> let -- SubtractionRegister
57 mem' = writeMem mem 8 ((readMem mem 8) - payload)
58 in
59 return state{ mem=mem' }
60 6 -> let -- MultiplicationRegister
61 mem' = writeMem mem 8 ((readMem mem 8) * payload)
62 in
63 return state{ mem=mem' }
64 7 -> let -- NegationRegister
65 mem' = if payload == 0 then writeMem mem 8 1 else writeMem mem 8 0
66 in
67 return state{ mem=mem' }
68 x -> do
69 return state{ mem=(writeMem mem x payload) }
70
71
72 beginTransaction x = x
73
74 commit x = x
75
76 commitAndRepeat x = x
77
78 rollback x = x
+86
-0
impl/ZOWIE.hs/src/Language/ZOWIE.hs less more
0 module Language.ZOWIE where
1
2 import qualified Data.Map.Strict as Map
3
4
5 type Addr = Integer
6 type Value = Integer
7 type Memory = Map.Map Addr Value
8
9 readMem mem addr = Map.findWithDefault 0 addr mem
10 writeMem mem addr value = Map.insert addr value mem
11
12 data Register = TtyRegister
13 | BeginTransactionRegister
14 | CommitRegister
15 | CommitAndRepeatRegister
16 | AdditionRegister
17 | SubtractionRegister
18 | MultiplicationRegister
19 | NegationRegister
20 | RegularRegister Addr
21
22 type CPU = Integer
23
24 data State = State {
25 cpu :: CPU,
26 mem :: Memory
27 } deriving (Show, Ord, Eq)
28
29
30 mapRegister 0 = TtyRegister
31 mapRegister 1 = BeginTransactionRegister
32 mapRegister 2 = CommitRegister
33 mapRegister 3 = CommitAndRepeatRegister
34 mapRegister 4 = AdditionRegister
35 mapRegister 5 = SubtractionRegister
36 mapRegister 6 = MultiplicationRegister
37 mapRegister 7 = NegationRegister
38 mapRegister x = RegularRegister x
39
40 readAddr :: State -> Addr -> IO Value
41 readAddr state@State{ cpu=cpu, mem=mem } addr =
42 case mapRegister addr of
43 TtyRegister -> do
44 i <- readLn
45 return i
46 BeginTransactionRegister -> return 1
47 CommitRegister -> return 2
48 CommitAndRepeatRegister -> return 3
49 AdditionRegister -> return 4
50 SubtractionRegister -> return 5
51 MultiplicationRegister -> return 6
52 NegationRegister -> return 7
53 RegularRegister x -> return (readMem mem x)
54
55 writeAddr :: State -> Addr -> Value -> IO State
56 writeAddr state@State{ cpu=cpu, mem=mem } addr payload =
57 case mapRegister addr of
58 TtyRegister -> do
59 print payload
60 return state
61 BeginTransactionRegister ->
62 return state{ cpu=(beginTransaction cpu) }
63 CommitRegister ->
64 return state{ cpu=(if payload > 0 then commit cpu else rollback cpu) }
65 CommitAndRepeatRegister ->
66 return state{ cpu=(if payload > 0 then commitAndRepeat cpu else commit cpu) }
67 AdditionRegister ->
68 return state{ mem=(writeMem mem 8 ((readMem mem 8) + payload)) }
69 SubtractionRegister ->
70 return state{ mem=(writeMem mem 8 ((readMem mem 8) - payload)) }
71 MultiplicationRegister ->
72 return state{ mem=(writeMem mem 8 ((readMem mem 8) * payload)) }
73 NegationRegister ->
74 return state{ mem=(writeMem mem 8 (if payload == 0 then 1 else 0)) }
75 RegularRegister x ->
76 return state{ mem=(writeMem mem x payload) }
77
78
79 beginTransaction x = x
80
81 commit x = x
82
83 commitAndRepeat x = x
84
85 rollback x = x