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module Language.ZOWIE where
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import qualified Data.Map.Strict as Map
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type Addr = Integer
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type Value = Integer
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type Memory = Map.Map Addr Value
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readMem mem addr = Map.findWithDefault 0 addr mem
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writeMem mem addr value = Map.insert addr value mem
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data Register = TtyRegister
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| BeginTransactionRegister
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| CommitRegister
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| CommitAndRepeatRegister
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| AdditionRegister
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| SubtractionRegister
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| MultiplicationRegister
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| NegationRegister
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| RegularRegister Addr
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type CPU = Integer
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data State = State {
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cpu :: CPU,
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mem :: Memory
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} deriving (Show, Ord, Eq)
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mapRegister 0 = TtyRegister
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mapRegister 1 = BeginTransactionRegister
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mapRegister 2 = CommitRegister
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mapRegister 3 = CommitAndRepeatRegister
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mapRegister 4 = AdditionRegister
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mapRegister 5 = SubtractionRegister
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mapRegister 6 = MultiplicationRegister
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mapRegister 7 = NegationRegister
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mapRegister x = RegularRegister x
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readAddr :: State -> Addr -> IO Value
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readAddr state@State{ cpu=cpu, mem=mem } addr =
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case mapRegister addr of
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TtyRegister -> do
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i <- readLn
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return i
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BeginTransactionRegister -> return 1
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CommitRegister -> return 2
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CommitAndRepeatRegister -> return 3
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AdditionRegister -> return 4
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SubtractionRegister -> return 5
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MultiplicationRegister -> return 6
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NegationRegister -> return 7
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RegularRegister x -> return (readMem mem x)
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writeAddr :: State -> Addr -> Value -> IO State
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writeAddr state@State{ cpu=cpu, mem=mem } addr payload =
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case mapRegister addr of
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TtyRegister -> do
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print payload
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return state
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BeginTransactionRegister ->
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return state{ cpu=(beginTransaction cpu) }
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CommitRegister ->
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return state{ cpu=(if payload > 0 then commit cpu else rollback cpu) }
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CommitAndRepeatRegister ->
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return state{ cpu=(if payload > 0 then commitAndRepeat cpu else commit cpu) }
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AdditionRegister ->
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return state{ mem=(writeMem mem 8 ((readMem mem 8) + payload)) }
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SubtractionRegister ->
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return state{ mem=(writeMem mem 8 ((readMem mem 8) - payload)) }
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MultiplicationRegister ->
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return state{ mem=(writeMem mem 8 ((readMem mem 8) * payload)) }
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NegationRegister ->
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return state{ mem=(writeMem mem 8 (if payload == 0 then 1 else 0)) }
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RegularRegister x ->
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return state{ mem=(writeMem mem x payload) }
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beginTransaction x = x
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commit x = x
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commitAndRepeat x = x
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rollback x = x
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